Essential Terms

A mechanism in multiprocessor systems that ensures all caches maintain a consistent view of shared memory. When one core modifies a cached memory location, coherence protocols update or invalidate stale copies in other caches so that future reads observe the correct value.

The CPU looks for a piece of data in the ultra-fast cache memory, finds it immediately, and reads it with minimal latency.

The CPU looks for data in the cache, doesn't find it, and is forced to drop down to slower main memory (RAM) to fetch it, creating a costly performance penalty.

The physical latency window or time lag required for a carry bit to travel and stabilize through a chain of adders. In a Ripple Carry Adder, Full Adder 4 cannot calculate its final Sum until Full Adders 1, 2, and 3 have sequentially completed their operations and passed the carry bit down the wire.

Occurs when the processor cannot determine the next instruction to fetch because the outcome of a branch, jump, or conditional instruction has not yet been resolved.