CS301: Resources | Saylor Academy

Topic	Name	Description
	Course Syllabus

© Saylor Academy 2010-2024 except as otherwise noted. Excluding course final exams, content authored by Saylor Academy is available under a Creative Commons Attribution 3.0 Unported license. Third-party materials are the copyright of their respective owners and shared under various licenses. See detailed licensing information. Saylor Academy®, Saylor.org®, and Harnessing Technology to Make Education Free® are trade names of the Constitution Foundation, a 501(c)(3) organization through which our educational activities are conducted.

Course Introduction

Course Syllabus

Unit 1: Introduction to Computer Technology

1.1: Introduction to Computer Processors

1.2: Components of a Computer

1.3: The Role of Processor Performance

1.4: The Power Problem

1.5: The Switch to Parallel Processing

1.6: Case Study: A Recent Intel Processor

Unit 1 Assessment

Unit 2: Instructions: Hardware Language

2.1: Computer Hardware Operations

2.2: Number Representation in Computers

2.3: Instruction Representation

2.4: Logical and Arithmetic Instructions

2.5: Control Instructions

2.6: Instructions for Memory Operations

2.7: Different Modes for Addressing Memory

2.8: Case Study: Intel and ARM Instructions

Unit 2 Assessment

Unit 3: Fundamentals of Digital Logic Design

3.1: Beginning Design: Logic Gates, Truth Table, and Logic Equations

3.2: Combinational Logic

3.3: Flip-Flops, Latches, and Registers

3.4: Sequential Logic Design

3.5: Case Study: Design of a Finite State Machine (FSM) to Control a Vending Machine

Unit 3 Assessment

Unit 4: Computer Arithmetic

4.1: Number Representation

4.2: Addition and Subtraction Hardware

4.3: Multiplication

4.4: Floating Point Arithmetic

4.5: Division

4.6: Case Study: Floating Point Arithmetic in an x86 Processor

Unit 4 Assessment

Unit 5: Designing a Processor

5.1: Von Neumann Architecture

5.2: Simple MIPS Processor Components

5.3: Designing a Datapath for a Simple Processor

5.4: Alternative Approach to Datapath Design and Design of a Control for a Simple Processor

5.5: Pipelining and Hazards

5.6: Pipelined Processors

5.7: Instruction-Level Parallelism

Unit 5 Assessment

Unit 6: The Memory Hierarchy

6.1: Elements of Memory Hierarchy and Caches

6.2: Cache Architectures and Improving Cache Performance

6.3: Main Memory and Virtual Memory

6.4: Performance Tuning

Unit 6 Assessment

Unit 7: Storage and I/O

7.1: I/O Devices

7.2: Connecting I/O Devices to the Processor

7.3: Measuring Disk Performance

7.4: Redundant Array of Inexpensive Disks (RAID)

Unit 7 Assessment

Unit 8: Parallel Processing

8.1: The Reason for the Switch to Parallel Processing

8.2: Limitations in Parallel Processing: Amdahl's Law

8.3: Shared Memory and Distributed Memory Multiprocessing

8.4: Multicore Processors and Programming with OpenMP and MPI

Unit 8 Assessment

Unit 9: Look Back and Look Ahead

9.1: Theory and Laws

9.2: Special Purpose Computing Architectures

9.3: Case Study: Special Purpose Applications of Parallel Computing

Unit 9 Assessment

Course Feedback Survey

Certificate Final Exam

Archived Materials