## MIPS Instructions

Read this article for an introduction to the three different instruction formats for the MIPS processor: the R-Format, the I-Format, and the J-Format instructions. MIPS is an acronym that stands for Microprocessor Instructions without Interlocked Pipeline Stages. MIPS is a RISC (Reduced Instruction Set Computer) introduced by MIPS technologies. Also, ISA, if you encounter it, stands for Instruction Set Architecture.

#### R Instructions

R instructions are used when all the data values used by the instruction are located in registers.

All R-type instructions have the following format:

OP rd, rs, rt


Where "OP" is the mnemonic for the particular instruction. rs, and rt are the source registers, and rd is the destination register. As an example, the add mnemonic can be used as:

add $s1,$s2, $s3  Where the values in$s2 and $s3 are added together, and the result is stored in$s1. In the main narrative of this book, the operands will be denoted by these names.

##### R Format

Converting an R mnemonic into the equivalent binary machine code is performed in the following way:

 opcode rs rt rd shift (shamt) funct 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

opcode

The opcode is the machinecode representation of the instruction mnemonic. Several related instructions can have the same opcode. The opcode field is 6 bits long (bit 26 to bit 31).

rs, rt, rd

##### I Format

I instructions are converted into machine code words in the following format:

 opcode rs rt IMM 6 bits 5 bits 5 bits 16 bits

Opcode

The 6-bit opcode of the instruction. In I instructions, all mnemonics have a one-to-one correspondence with the underlying opcodes. This is because there is no funct parameter to differentiate instructions with an identical opcode. 6 bits (26 to 31)

rs, rt

The source and target register operands, respectively. 5 bits each (21 to 25 and 16 to 20, respectively).

IMM

The 16 bit immediate value. 16 bits (0 to 15). This value is usually used as the offset value in various instructions, and depending on the instruction, may be expressed in two's complement.

#### J Instructions

J instructions are used when a jump needs to be performed. The J instruction has the most space for an immediate value, because addresses are large numbers.

J instructions are called in the following way:

OP LABEL


Where OP is the mnemonic for the particular jump instruction, and LABEL is the target address to jump to.

##### J Format

J instructions have the following machine-code format:

Opcode

The 6 bit opcode corresponding to the particular jump command. (26 to 31).

A 26-bit shortened address of the destination. (0 to 25). The two least significant bits are removed, and the 4 most significant bits are removed, and assumed to be the same as the current instruction's address.

#### FR Instructions

FR instructions are similar to the R instructions described above, except they are reserved for use with floating-point numbers:

 Opcode fmt ft fs fd funct

#### FI Instructions

FI instructions are similar to the I instructions described above, except they are reserved for use with floating-point numbers:

 Opcode fmt ft Imm

Opcodes

The following table contains a listing of MIPS instructions and the corresponding opcodes. Opcode and funct numbers are all listed in hexadecimal.

Mnemonic Meaning Type Opcode Funct
add Add R 0x00 0x20
addi Add Immediate I 0x08 NA
addiu Add Unsigned Immediate I 0x09 NA
addu Add Unsigned R 0x00 0x21
and Bitwise AND R 0x00 0x24
andi Bitwise AND Immediate I 0x0C NA
beq Branch if Equal I 0x04 NA
blez Branch if Less Than or Equal to Zero I 0x06 NA
bne Branch if Not Equal I 0x05 NA
bgtz Branch on Greater Than Zero I 0x07 NA
div Divide R 0x00 0x1A
divu Unsigned Divide R 0x00 0x1B
j Jump to Address J 0x02 NA
jal Jump and Link J 0x03 NA
jr Jump to Address in Register R 0x00 0x08
lb Load Byte I 0x20 NA
lbu Load Byte Unsigned I 0x24 NA
lhu Load Halfword Unsigned I 0x25 NA
lui Load Upper Immediate I 0x0F NA
lw Load Word I 0x23 NA
mfhi Move from HI Register R 0x00 0x10
mthi Move to HI Register R 0x00 0x11
mflo Move from LO Register R 0x00 0x12
mtlo Move to LO Register R 0x00 0x13
mfc0 Move from Coprocessor 0 R 0x10 NA
mult Multiply R 0x00 0x18
multu Unsigned Multiply R 0x00 0x19
nor Bitwise NOR (NOT-OR) R 0x00 0x27
xor Bitwise XOR (Exclusive-OR) R 0x00 0x26
or Bitwise OR R 0x00 0x25
ori Bitwise OR Immediate I 0x0D NA
sb Store Byte I 0x28 NA
sh Store Halfword I 0x29 NA
slt Set to 1 if Less Than R 0x00 0x2A
slti Set to 1 if Less Than Immediate I 0x0A NA
sltiu Set to 1 if Less Than Unsigned Immediate I 0x0B NA
sltu Set to 1 if Less Than Unsigned R 0x00 0x2B
sll Logical Shift Left R 0x00 0x00
srl Logical Shift Right (0-extended) R 0x00 0x02
sra Arithmetic Shift Right (sign-extended) R 0x00 0x03
sub Subtract R 0x00 0x22
subu Unsigned Subtract R 0x00 0x23
sw Store Word I 0x2B NA

Source: Wikibooks, https://en.wikibooks.org/wiki/MIPS_Assembly/Instruction_Formats