Read this article to learn about arithmetic and logical instructions for the MIPS processor.

add 

R Type 
This instruction adds the two operands together, and stores the result in the destination register. Negative numbers are handled automatically using two's complement notation, so different instructions do not need to be used for signed and unsigned numbers.

sub 

R Type 
The sub instruction subtracts the second source operand from the first source operand, and stores the result in the destination operand. In pseudocode, the operation performs the following:
rd := rs  rt
Both add and sub trap if overflow occurs. However, some programming systems, like C, ignore integer overflow, so to improve performance "unsigned" versions of the instructions don't trap on overflow.

addu 

R Type 

subu 

R Type 
The multiply and divide operations are slightly different from other operations. Even if they are Rtype operations, they only take 2 operands. The result is stored in a special 64bit result register. We will talk about the result register after this section.

mult 

R Type 
This operation multiplies the two operands together, and stores the result in rd. Multiplication operations must differentiate between signed and unsigned quantities, because the simplicity of Two's Complement Notation does not carry over to multiplication. The
mult instruction multiplies and sign extends signed numbers.
The result of multiplying 2 32bit numbers is a 64bit result. We will discuss the 64bit results below.

multu 

R Type 
The multu instruction multiplies the two operands together, and stores the result in rd. This instruction is for unsigned numbers only, and does not sign extend a negative result. This operation also creates a 64bit result.

div 

R Type 
The div instruction divides the first argument by the second argument. The quotient is stored in the lowest 32bits of the result register. The remainder is stored in the highest 32bits of the result register. Like multiplication, division requires a differentiation between signed and unsigned numbers. This operation uses signed numbers.

divu 

R Type 
Like the div instruction, this operation divides the first operand by the second operand. The quotient is stored in the lowest 32bits of the result, and the remainder is stored in the highest 32bits of the result. This operand divides unsigned numbers, and will not signextend the result.
The 64bit result register is broken into two 32bit segments: HI and LO. We can interface with these registers using the mfhi and mflo operations, respectively.

mfhi 

R Type 
Takes only 1 operand. This instruction moves the high32 bits of the result register into the target register.

mflo 

R Type 
Also takes only 1 operand. Moves the value from the LO part of the result register into the specified register.
If the upper (most significant) 32 bits of a product are unimportant to computation, programmers may save a step by using instructions that discard the upper 32 bits.

mul 

R Type 
There is no unsigned version of the mul instruction. The mul instruction may also clobber the existing values in HI and LO.
These operations perform bitwise logical operations on their operands.

and 

R Type 
Performs a bitwise AND operation on the two operands, and stores the result in rd.

or 

R Type 
Performs a bitwise OR operation on the two operands, and stores the result in rd.

nor 

R Type 
Performs a bitwise NOR operation on the two operands, and stores the result in rd.

xor 

R Type 
Performs a bitwise XOR operation on the two operands, and stores the result in rd.
These instructions signextend the 16bit immediate value to 32bits and performs the same operation as the instruction without the trailing "i".

addi 

I Type 

addiu 

I Type 
To subtract, use a negative immediate.
All logical functions zeroextend the immediate.

andi 

I Type 
Takes the bitwise AND of rs with the immediate and stores the result in rt.

ori 

I Type 
Takes the bitwise OR of rs with the immediate and stores the result in rt.

xori 

I Type 
Takes the bitwise XOR of rs with a the immediate and stores the result in rt.

sll 

R Type 
Logical shift left: rd ← rt << shamt. Fills bits from right with zeros.

srl 

R Type 
Logical shift right: rd ← rt >> shamt. Fills bits from left with zeros.

sra 

R Type 
Arithmetic shift right. If rt is negative, the leading bits are filled in with ones instead of zeros: rd ← rt >> shamt.
Because not all shift amounts are known in advance, MIPS defines versions of these instructions that shift by the amount in the rs register. The behavior is otherwise identical.

sllv 

R Type 

srlv 

R Type 

srav 

R Type 
Source: Wikibooks, https://en.wikibooks.org/wiki/MIPS_Assembly/Arithmetic_Instructions
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